Circuit for generating a column selection control signal in a memory device

专利摘要:
The column selection control signal generation circuit of the memory device according to the present invention comprises: a column selection control signal control block for generating a column selection control signal for the normal operation of the first cycle of the page mode; A latch for setting and outputting a column selection control signal from the column selection control signal control block; A read reset block for resetting the latch; A page read column select control signal enable block configured to generate and set a column select control signal to the latch as the page address changes when the page read mode is operated in the page read mode; And a page read reset block for resetting the latch set by the page read column selection control signal enable block.
公开号:KR20040007027A
申请号:KR1020020041658
申请日:2002-07-16
公开日:2004-01-24
发明作者:최정균
申请人:주식회사 하이닉스반도체；
IPC主号:

专利说明:

Circuit for generating a column selection control signal in a memory device
[24] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a column selection control signal of a memory device. In particular, the present invention relates to a memory device for performing a page mode operation among memory devices for which read and write speeds are increased. The present invention relates to a column control signal generating circuit that can be used.
[25] There are several modes to speed up the read and write data in the memory device.
[26] Among memory devices recently developed for mobile, page read mode exists to improve read speed, but employs page write mode to improve write speed. There are no devices. Accordingly, there is a need for a structure capable of generating a column control signal (Yi Control) that operates in a page write mode corresponding to a page read mode.
[27] In general memory devices, a row address is used to select a specific word line among a plurality of word lines. When the word line is selected, the data in the memory cell is charged and shared on the bit line, and the charged shared microsignal is transferred to the bit line sense amplifier. Amplifies to a level with full swing width. This state is called an active state, and this path is called a low path.
[28] In addition, the column address serves to select one memory cell among a plurality of memory cells connected to a specific word line selected by a row address and output data on the bit line to the outside. This path is called a column path. In general, when comparing the path difference between the row path and the column path, the path is longer in the row path, which consumes a lot of time.
[29] Therefore, in order to perform a more efficient read or write operation on the memory device, the concept of a page mode has been considered. In other words, the concept of page refers to memory cells sharing the same word line, and 4 words and 8 words according to the length of the page operation among the shared memory cells. It is divided into 16 words (Words), full page (Full Page), etc. Since the same word line is shared, the row address is the same and only the column address is different.
[30] Therefore, when storing or writing data to a memory cell, a row path with a long path is performed only once the first time. Instead of performing a row path operation and a column path operation each time, the word line is executed only once. In this state, the column path operation is performed at high speed by changing only the column address.
[31] FIG. 1A illustrates a Yi Control Scheme of a column selection control signal structure of a memory device operating in a conventional normal operation mode, and the column selection control signal control block illustrated in FIG. 10) a word line clear bar signal (Wlcb) and a control signal (Sg; Sensing Generator-signal of the same path as the Wlcb signal in the same path as delayed by the delay unit 30). In combination to generate a column select control signal (Yi-Control), and the pulse control block (Pulse Control Block) 20 shown in FIG. 1B is a column select control signal (Yi-Control) when the read signal is high. When the read signal is low, the column select control signal (Yi-Control) is generated at the level.
[32] Since the structure as shown in FIG. 1A does not include the page mode, the page write mode cannot be performed.
[33] Accordingly, an object of the present invention is to provide a circuit capable of generating a column control signal (Yi Control) that operates in a page write mode corresponding to a page read mode.
[1] 1A is a circuit diagram of generating a column selection control signal in a conventional general operation mode.
[2] FIG. 1B is a detailed circuit diagram of the column select signal control block of FIG. 1A.
[3] FIG. 1C is a detailed circuit diagram of the pulse control block of FIG. 1A.
[4] 2 is a circuit diagram of generating a column selection control signal in the page read mode according to the present invention.
[5] 3 is a circuit diagram of generating a column selection control signal in the page write mode according to the present invention.
[6] 4 is a circuit diagram of generating a column selection control signal in the page read and write modes according to the present invention.
[7] 5 is a circuit diagram for generating a column selection control signal in a page read and normal operation mode according to the present invention.
[8] 6 is a circuit diagram of generating a column selection control signal in a page write and normal operation mode according to the present invention.
[9] 7 is a circuit diagram for generating a column selection control signal in a page read, write, and normal operation mode according to the present invention.
[10] 8A is a detailed circuit diagram of a page read column selection control signal enable block.
[11] 8B is a detailed circuit diagram of a page write column selection control signal enable block.
[12] 8C is a detailed circuit diagram of the read reset block.
[13] 8D is a detailed circuit diagram of the page read reset block.
[14] 8E is a detailed circuit diagram of the page write reset block.
[15] 9 is an operation timing diagram in page read mode.
[16] 10 is an operation timing diagram in a page write mode.
[17] * Explanation of symbols for the main parts of the drawings
[18] 10: column select signal control block 20: pulse control block
[19] 30: first delay unit 40: second delay unit
[20] 50: lead reset block 60: page lead reset block
[21] 70: first pulse generator
[22] 90: page lead column select control signal enable block
[23] 120: Page light column selection control signal enable block
[34] According to the present invention, when the first cycle of the page read mode (the address other than the page address and the page address changes simultaneously) to implement the page read mode, the page mode is used. In the first cycle of), the column select control signal (Yi) is controlled by pulse using the same path signal as the signal used to enable the word line. In the situation where only the page address is changed, a page address transition detection (Page ATD) signal is generated by the page address change, and the signal is used to control the column selection control signal (Yi) with a pulse. Column path operation can be performed at high speed within the same page.
[35] In order to implement the page write mode, the first cycle (the address other than the page address and the page address) is changed at the same time as the page read mode. In the first cycle of the mode), the column selection control signal (Yi) is controlled to the level using the same path signal as the signal used to enable the word line. In a situation where only a page address is changed within the page, a column control signal column (Yi: Column Address Select) is controlled at a level by controlling the write enable signal (/ WE), which is an external control signal, when the page address changes. By doing so, the column path operation can be performed at the same speed within the same page.
[36] Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
[37] 2 illustrates an embodiment of a column control signal control structure (Yi Control Scheme) used in the page read mode corresponding to the present invention.
[38] In the first cycle of Page Read Mode of this circuit (the first cycle of Page Mode is when the address of the page address and other than the page address are changed at the same time), as in the conventional way, By the column select signal control block 10 shown in FIG. The column select control signal (Yi-Control) is generated by a combination of a signal having only a time delay. However, the difference is that the level signal Sg is used in a conventional circuit. This signal (sg) transitions from low to high for a path that resets the latch 500 again because only the column path must be continuously performed in the floating state. When used for the first pulse generator (70) to make a high pulse (Pulse High).
[39] A read reset block 50 for resetting the latch 500 set by the column select signal control block 10 is required. This block receives the Sg signal as shown in FIG. 8C and generates a high pulse in the second pulse generator 80 when the signal transitions from high to low, and this high pulse and the write enable bar signal (/ WE). Is combined by the NAND gate ND1, that is, when the Web (Write Enable Bar) is low, the reset signal is prevented, and the reset signal is generated only when the Web is high. That is, the output signal of the NAND gate ND1 is delayed by the delay unit 100, and the PMOS transistor P1 is turned on or off by the output signal of the delay unit 100 to generate a reset signal.
[40] When the page read column select control signal enable block 90 is finished after the first cycle of the page read mode, only the page address is changed in the same page. As shown in FIG. 8A, a column selection control signal (Yi-Control) is generated by a combination of a Read (signal indicating the read mode) signal and a Page ATD (Address Transition Detector) indicating that the page address has been changed. . In addition, a page read reset block 60 as shown in FIG. 8D has been placed to reset the latch 500 set by this block 90. The block 60 is a signal generated by a combination of a read signal and a page ATD signal is passed through the delay unit 100.
[41] FIG. 9 is a timing diagram in which the circuit of FIG. 2 continuously performs a page read mode. In the first cycle of the page mode, a row path operation and a column path ( Because it executes Column Path (simultaneously) column operation, it needs time as much as tRC (Read Cycle Time), and in subsequent cycles it takes only as much as tPRC (Page Read Cycle Time) needed to perform column path operation. It is shown.
[42] 3 illustrates an embodiment of a column selection control signal control structure used in a page write mode corresponding to the present invention. In the first cycle of the page write mode of this circuit (the first cycle of the page mode is when the address other than the page address and the page address are changed simultaneously) as shown in Fig. Select column by combination of wlcb (Word Line Clear Bar) signal and Sg (Sensing Generator-same signal as Timing Delay signal with Wlcb signal) by the column select signal control block (Yi Control Block) The control signal (Yi-Control) signal is generated, except that the conventional circuit uses the Sg signal, which is a level signal, and in the present invention, since only the column path must be continuously performed while the word line is floating. For the path to reset latch 500 again, use a third pulse generator 110 that outputs a high pulse when this signal transitions from low to high. The.
[43] In addition, the page write column select control signal enable block 120 shown in FIG. 8B ends the first cycle of the page write mode and the page address within the same page. When only the address) is changed, as shown in the timing diagram of the embodiment shown in Fig. 10, the write enable bar signal / WE is controlled at a certain time interval with the page address transition to receive the signal, and the Web When transitioning from high to low, the fourth pulse generator 130 generates a high pulse to generate a column select control signal (Yi-Control). In order to reset the latch 500 set in the block 120, a page write reset block 100 as shown in FIG. 8E is provided. This block 100 was used to create a low pulse by the fifth pulse generator 140 when the Web signal transitions from low to high.
[44] FIG. 10 is a timing diagram in which the circuit shown in FIG. 3 continuously performs the page write mode. In the first cycle of the page mode, since the row path operation and the column path operation are simultaneously performed, tWC (Write) is shown. Cycle Time) is required, and subsequent cycles take only as long as the Page Write Cycle (tPWC) required to perform the column path operation.
[45] FIG. 4 is a structure of generating a column select control signal (Yi-Control) designed to operate simultaneously in a page read mode and a page write mode. In this circuit, a column select signal control block (Yi-Control Block) 10, a read reset block 50, and a page read column select control signal enable block (3) having the same functions as those described with reference to Figs. Page Read Yi Enable Block (90), Page Read Reset Block (60), Page Write Column Select Control Signal Enable Block (Page Write Yi Enable Block; 120), Page Write Reset Block (Page Write Reset Block) 100 are used in a memory device in which a page read mode and a page write mode are simultaneously used.
[46] FIG. 5 is a circuit block for creating a column selection control signal (Yi-Control) that can be employed in a memory device supporting both a page read mode and a normal operation mode. The circuit includes a column select control signal control block (Yi Control Block) 10, a read reset block (50), and a page read column select control signal enable block (Page Read) that perform the same functions as described in FIG. Yi Enable Block; 90), Page Read Reset Block (60), and so on to operate in Page Read Mode.In addition, when in Read Mode in Normal Operation Mode, A pulse control block 20 is provided to make a column select control signal (Yi-Control) into a pulse and to write a column select control signal (Yi-Control) to a level in a write operation. . This circuit performs the same function as described in FIG. 2 in the page read operation.
[47] FIG. 6 is a circuit block for creating a column selection control signal that can be employed in a memory device supporting both a page write mode and a normal operation mode. The circuit includes a column select control signal control block (Yi Control Block) 10, a page write column select control signal enable block (Page Write Yi Enable Block) 120, and a page write reset block which perform the same functions as described in FIG. (Page Write Reset Block; 100), etc. to operate in Page Write Mode.In addition, in case of read operation in Normal Operation Mode, it pulses the column select control signal (Yi-Control). In the write operation, a pulse control block (20) is used to make the column selection control signal to a level. This circuit performs the same function as described in FIG. 3 in the page write operation.
[48] FIG. 7 is a block for generating a column selection control signal (Yi) designed to operate in a page read mode, a page write mode, and a normal operation mode. In this circuit, a column selection control signal control block (Yi Control Block), a read reset block, a page read column selection control signal enable block (Page Read Yi Enable) having the same function as described in FIGS. Block 90; page read reset block 60; page write column select control signal enable block 120; page write reset block 100; page write reset block 100; In addition, it operates in Page Read Mode and Page Write Mode.In addition, when read operation is performed in Normal Operation Mode, the column selection control signal is pulsed and write operation is performed. In the present invention, a pulse generation control block 20 is used to make the column selection control signal Yi level. This circuit performs the same function as described with reference to FIGS. 2 and 3 in the page read and page write modes.
[49] By using the circuit of the present invention, a memory device operating in the page read and page write modes can be implemented.
[50] Although the present invention has been described with reference to the embodiments, one of ordinary skill in the art can modify and change various forms using such embodiments, and thus the present invention is not limited to these embodiments. It is limited by the claims.

权利要求:
Claims (12)
[1" claim-type="Currently amended] A column select signal control block for generating a column select control signal for the normal operation of the first cycle of the page mode;
A latch for setting and outputting a column selection control signal from the column selection signal control block;
A read reset block for resetting the latch;
A page read column select control signal enable block configured to generate and set a column select control signal to the latch as the page address changes when the page read mode is operated in the page read mode;
And a page read reset block for resetting the latch set by the page read column select control signal enable block.
[2" claim-type="Currently amended] A column select control signal control block for generating a column select control signal for the normal operation of the first cycle of the page mode;
A latch for setting and outputting a column selection control signal from the column selection control signal control block;
A page write enable block configured to generate a column select control signal as the write enable bar signal is enabled in the page write mode;
A latch for latching and outputting a column select control signal from the page write enable block;
And a page write reset block for resetting the latch in the page write mode.
[3" claim-type="Currently amended] A column select control signal control block for generating a column select control signal for normal operation of the first cycle of the page mode;
A read reset block for resetting the latch set by the column select control signal control block;
A page read column select control signal enable block for generating a column select control signal as the page address changes when operating in the page read mode;
A page read reset block for resetting a latch set by the column select control signal enable block;
A page write column selection control signal enable block for generating a column select control signal as the write enable bar signal is enabled in the page write mode;
And a page write reset block for resetting the latch set by the page write column select control signal enable block.
[4" claim-type="Currently amended] The method of claim 3, wherein
The column select control signal control block generates a column select control signal according to an output of a pulse generator that generates a high pulse when the word line clear bar signal and the first control signal transition from low to high. Column selection control signal generation circuit.
[5" claim-type="Currently amended] The method of claim 1,
The read reset block combines a signal generated when the first control signal transitions from high to low and a write enable bar signal, and generates a reset signal when the two signals are high. Signal generating circuit.
[6" claim-type="Currently amended] The method according to claim 1 or 3,
Wherein the page read column selection control signal enable lock is configured to generate a column selection control signal by a combination of a signal indicating page read and a page address transition detection signal generated as the page address transitions. Selective control signal generation circuit.
[7" claim-type="Currently amended] The method according to claim 1 or 3,
The page read reset block may be configured to delay a signal generated by a combination of a signal indicating a read mode and an address transition detection signal generated as the page address transitions, thereby generating a page reset signal. Control signal generation circuit.
[8" claim-type="Currently amended] The method according to claim 2 or 3,
The page write column select control signal enable block may be configured to generate a column select control signal according to an output of a pulse generator that generates a high pulse when a write enable bar signal transitions from high to low. Column selection control signal generation circuit.
[9" claim-type="Currently amended] The method according to claim 2 or 3,
And the page write reset block is configured to generate a reset signal according to an output of a pulse generator that generates a low pulse when the write enable bar signal transitions from low to high.
[10" claim-type="Currently amended] A column select control signal control block for generating a column select control signal for the normal operation of the first cycle of the page mode;
A read reset block 위한 for resetting the latch set by the column select control signal control block;
A page read column select control signal enable block for generating a column select control signal as the page address is changed when operating in the page read mode;
And a page read reset block for resetting the latch set by the page read column select control signal enable block.
[11" claim-type="Currently amended] A column select control signal control block for generating a column select control signal for the normal operation of the first cycle of the page mode;
A page write column selection control signal enable block configured to generate a column select control signal as the write enable bar signal is enabled in the page write mode;
And a page write reset block for resetting the latch set in the page write mode.
[12" claim-type="Currently amended] A column select control signal control block for generating a column select control signal for the normal operation of the first cycle of the page mode;
A read reset block for resetting the latch set by the column select control signal control block;
A page read column select control signal enable block for generating a column select control signal as the page address changes when operating in the page read mode;
A page read reset block for resetting the latch set by the page column select control signal enable block;
A page write column selection control signal column selection control signal block for generating a column selection control signal as the write enable bar signal is enabled in the page write mode;
And a page write reset block for resetting the latch set by the page write column select control signal enable block.

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同族专利:

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公开号 | 公开日

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US20040015663A1|2004-01-22|

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KR100482766B1|2005-04-14|

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US7032084B2|2006-04-18|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
2002-07-16|Application filed by 주식회사 하이닉스반도체

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2002-07-16|Priority to KR20020041658A

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2004-01-24|Publication of KR20040007027A

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2005-04-14|Application granted

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2005-04-14|Publication of KR100482766B1

优先权:

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申请号 | 申请日 | 专利标题

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KR20020041658A|KR100482766B1|2002-07-16|2002-07-16|Circuit for generating a column selection control signal in a memory device|